pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 74

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
4.1.6
A read bus cycle starts at T1; at this point, the address is placed on the address bus, SELn (or SELIO) is activated and
WR0-1 are inactive, indicating that this is a read bus cycle. The RD signal is activated on the first TIW or T2 (when there are
no TIW cycles).
At the end of T2, the BIU samples the data on D0-7 or D0-15, according to BW signal in SZCFGn register. After T2, the
number of T
first T
hold
Bus State
Normal Read Bus Cycle
Bus State
cycle. The address remains valid until the end of the last T
WR0-1
A0-20
CLK
A0-20
SELn
D0-15
RD
BST0-2
CLK
SELIO
D0-15
RD
WR0-1
BST0-2
SEL0-2,
hold
cycles specified by HOLD in SZCFGn register (may be 0) is added. SELn and RD are deactivated on the
Figure 15. Late Write Bus Cycle Between Normal Read Bus Cycles with 0 Wait
Figure 16. Late Write Bus Cycle with 1 Internal Wait and 1 Hold
T1
Normal Read
T1
TIW
T2
(Continued)
In
T2
T1
74
Late Write
Out
hold
T hold
T2
Out
cycle.
T1
Normal Read
T2
In
Revision 1.2