pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 213

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
Software Method 2. Enable the hardwired frequency setting (M and N are set to generate a 96 MHz OSCCLK). Either a
normal or fast clock setting may be used. The programmable pre-scaler of the core domain clock is set according to the
HFCGP register; see “PMC Enabled SuperI/O Disabled State” on page 213.
During a frequency change, the OSCCLK output is low to prevent the system from using an unstable clock.
The HFCG is designed to be tightly coupled with the PMC. The HFCG receives two enable signals: one from the PMC and
the other from the host domain. The PMC can enable or disable core domain clock generation while in Idle mode; it enables
the core domain clock in Active mode. The SuperI/O configuration enables or disables clock generation for the host domain
according to the host processor requests.
4.18.3 HFCG States
There are three groups of HFCG states:
Transitions between the states are controlled by either hardware or firmware. Figure 75 shows the states and the hardware
or software transitions between them. Some of the software settings and transitions are protected to improve the system’s
durability with regard to software errors; see details in the following sections.
PMC Enabled SuperI/O Disabled State
Normal Clock Setting. This operation enables changing the clock frequency while in PMC Enabled SuperI/O Disabled
state or switching from SuperI/O Enabled PMC Enabled state to PMC Enabled SuperI/O Disabled state.
To change the OSCCLK frequency, load the N and M variables with new values. M is loaded in two parts by writing to
HFCGML and HFCGMH registers.
Load the new setting (N and M values, simultaneously) into the frequency multiplier. The core writes the new variables into
a data input buffer. Then a command loads the new values into the frequency multiplier. The command also loads simulta-
neously the programmable pre-scaler with 0 (set to a divide by 1). Note that HFCGP register does not change its contents.
To set a new clock frequency:
1. Write the N value to HFCGN register.
2. Write the low byte of the M value to HFCGML register.
3. Write the upper bits of the M value to HFCGMH register.
4. Set LOAD in the HFCGCTRL1 register to 1.
• PMC Enabled SuperI/O Disabled: OSCCLK is programmable (set by hardware or by software method 1). The core
• SuperI/O Enabled PMC Enabled/Disabled: OSCCLK is fixed at 96 MHz (set by hardware or by software method 2).
• Disabled: OSCCLK is disabled. Both core domain clock and host domain clock are disabled.
domain clock is enabled; the host domain clock is disabled.
The host domain clock is enabled; the core domain clock is either enabled or disabled depending on PMC.
Software Transitions
Hardware Transitions
SuperI/O
Disabled
SuperI/O Enabled
PMC Disabled
SuperI/O
Enabled
PMC
Disabled
Figure 75. HFCG States and Transitions
SuperI/O Disabled
PMC Enabled
PMC Disabled
PMC Enabled
Reload M, N, I
Disabled
(Continued)
PMC
Enabled
213
or Fast96
SuperI/O Enabled
Load96
Program Pre-Scaler
PMC Enabled
Load or Fast
May be done in response to
interrupt on SuperI/O Enabled
May be done in response to
interrupt on SuperI/O Disabled
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