pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 286

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Module
Wake-Up Event Status Register 0 (WK_STS0)
This register is set to 00
events, associated with the register, have occurred. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Bit 6 behaves in
a special way, as described in the table below.
Location: Offset 00
Type:
Wake-Up Events Enable Register (WK_EN0)
This register is set to 00
the PWUREQ signal is activated.
Location: Offset 02
Type:
Bit
Name
Reset
Bit
Name
Reset
5-4
Bit
0
1
2
3
6
7
RI1 Event Status.
0: Event not detected (default)
1: Event detected
RI2 Event Status.
0: Event not detected (default)
1: Event detected
Reserved.
RING Event Status. RING event detection, according to the RING detection mode enabled.
0: Event not detected (default)
1: Event detected
Reserved.
Software Event Status. This bit may work in two modes, as defined by HSECM bit in MSWCTL1 register (see
“MSWC Control Status Register 1 (MSWCTL1)” on page 291).
When HSECM is 0, writing 1 to Software Event Status bit inverts its value.
When HSECM is 1, writing 1 to Software Event Status bit sets it; the bit is cleared by a write of 1 to bit 6 in
MSHES0 register.
0: Event not active (default)
1: Event active
Module IRQ Event Status. This sticky bit shows the status of the module IRQ event detection.
0: Event not active (default)
1: Event active
R/W1C
R/W
Module IRQ
Module IRQ
Enable
Status
Event
Event
16
7
0
16
7
0
16
16
on V
on V
Software
Software
Enable
Status
Event
Event
PP
PP
6
0
6
0
power-up or Host Domain Software reset. When enabled wake-up events are detected,
power-up, V
5
0
5
0
CC
Reserved
Reserved
power-up or Host Domain Software reset. It indicates which wake-up
(Continued)
Description
286
4
0
4
0
Enable
Status
Event
Event
RING
RING
3
0
3
0
Reserved
Reserved
2
0
2
0
Enable
Status
Event
Event
RI2
RI2
1
0
1
0
Enable
Status
Event
Event
RI1
RI1
0
0
0
0
Revision 1.2