pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 28

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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1.0 Introduction
IRQ, SMI or SCI events to the host. The Power Management channels include a PC87570-compatible mode and an en-
hanced scheme that enables more efficient control by the core.
Shared Memory and Protection is supported between the host and the core. This sharing may be used for the support of
a shared BIOS scheme, for protected information storage and/or for the PC87591L-N05 firmware update by the host. The
expansion memory can be used as shared memory. The Shared Memory module provides means for the host to access the
shared memory. It can also protected access to portions of the shared memory for read and/or write operations to allow
reliable and tamper-protected storage and protected update.
The Mobile System Wake-Up module includes various system wake-up and power management services that may be han-
dled either by the host or the core. The wake-up sources may be the RTC or external events such as ring detection on the
RING input or modem RI inputs. The module provides hooks for ACPI-compliant drivers, which enable the drivers to handle
wake-up events, change the system power state (including turning it off) and interface to the core firmware. Mask bits can
be enabled to determine whether the core or the host handles each one of the events. In addition, this module provides sta-
tus information about the host domain (e.g., reset input state and V
The Core Access to Host-Controlled Peripherals module enables core access to SuperI/O modules. It can interleave us-
age of a module with the host or take control of it and prevent any host access to that module.
1.3.6
The Host Interface is based on Intel’s Low Pin Count (LPC) interface, as defined in LPC Interface Specification, Revision
1.1. This interface enables the host to perform read and write cycles using I/O space accesses and memory space accesses
and FWH transactions. Interrupts are sent to the host, using the serial IRQ protocol.
The PC87591L-N05 supports the advanced power management features of the LPC bus. The SMI signal may be sent to
interrupt the host and put it in System Management Mode (SMM). The PWUREQ signal may be connected to one of the
wake-up inputs of the host chipset and used to trigger an SCI event for various EC communication purposes. The
PC87591L-N05 can operate with a slowed down or stopped LPC clock and can re-start the LPC clock as part of the system
power management capabilities, using the CLKRUN signal. The LPCPD input enables turning off LPC bus supply while the
PC87591L-N05 and some Host Controlled functions are operating.
Host Configuration. The PC87591L-N05 includes a set of global configuration register and seven logical devices, each with
associated configuration registers.
The central configuration register set supports ACPI-compliant PnP configuration. The configuration registers are structured
as a subset of the Plug and Play Standard registers defined in Appendix A of the Plug and Play ISA Specification, Revision
1.0a by Intel and Microsoft. All system resources assigned to the functional blocks (I/O address space and IRQ lines) are
configured in and managed by the central configuration register set. In addition, some function-specific parameters are con-
figurable through the configuration registers and distributed to the functional blocks through special control signals.
The RTC (Real Time Clock) has a low-power timekeeping mechanism that provides a time-of-day, year-2000-compatible
calendar with a century counter and alarm features. It can work from either V
Other features include three maskable interrupt sources and 242 bytes of general-purpose RAM. An external battery source
maintains valid RAM and time during V
1.4
On Power-Up reset, the ENV1-0 and TRIS input signals select one of the following operating environments:
See Section 2.3 on page 48 for more information about these pins and controlling the loads connected to them.
Code written for IRE environment is executable in all environments, since it is binary compatible. The execution time of code
in on-chip base memory (in IRE environment) is identical to that in OBD and DEV environments; i.e., the operation is cycle-
by-cycle compatible.
The PC87591L-N05 is factory tested to ensure that it operates in either IRE or OBD environment. Only selected parts are
tested for operation in DEV environment.
1.4.1
IRE environment is used for PC87591L-N05 operation in the production system and for normal execution of applications.
The external flash is the main source of code for the device. In this environment, after reset, the PC87591L-N05 starts run-
ning the code written in the first address of the internal ROM.
The PC87591L-N05 is shipped with 4 Kbytes of on-chip boot code. The user is expected to use an external memory for most
of the code and constant data.
To maximize on-chip ROM performance, configure the BIU as described in Section 4.1.11 on page 84.
• Internal ROM Enabled (IRE)
• On Board Development (OBD)
• Development (DEV)
OPERATING ENVIRONMENTS
Host-Controlled SuperI/O Modules and Host Interface
IRE Environment
(Continued)
CC
failure. The RTC is software compatible with the DS1287 and MC146818.
28
DD
supply status).
CC
or a backup battery, using an internal switch.
Revision 1.2