pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 265

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
5.0 Host Controller Interface Modules
5.3.3
The following I/O mapped registers can be utilized instead of memory mapping to perform a core bus transaction using an
LPC I/O transaction:
An LPC I/O write to the IMD register triggers a core bus memory write cycle using the addresses and data from IMA3-IMA0
and IMD registers, respectively. The LPC I/O write is completed when the core bus transaction is completed.
An LPC I/O read cycle from IMD register triggers a core bus memory read cycle using the addresses from IMA3-IMA0. The
data returned from the core bus cycle is used to complete the LPC I/O read cycle from IMD register.
Read/write cycles from/to IMA3-IMA0 registers drive Short Wait on the Sync field. Read/write cycles from/to IMD register
drive Long Wait on the Sync field until a transaction is actually performed and completed on the core bus.
Indirect memory read/write transactions are subject to the same memory mapping, locking mechanism and host access pro-
tection as memory and FWH memory read/write transactions. For more details, see Sections 5.3.2, 5.3.4 and 5.3.5.
5.3.4
For read operations, hardware handles arbitration between the host and core. For expansion memory program and erase
operations, the PC87591L-N05 provides the means for enabling exclusive use for any particular access path over a se-
quence of operations.
• Four Indirect Memory Address registers (IMA3-IMA0), representing host address bits 31 to 0
• One Indirect Memory Data register (IMD), representing data bits 7 to 0
Indirect Memory Read and Write Transaction
Locking Between Domains
XXX1F FFFF
XXX10 0000
XXX00 0000
16
16
16
~ ~
~ ~
Figure 92. Host to Core Address Translation: Non-BIOS Mode
Host Address
1
~ ~
~ ~
(Continued)
265
Core Address
1
Numbers (1) indicate the links
between host memory and core
memory maps.
XXX1F FFFF
of the address are ‘1’
00 E000
1F FFFF
10 0000
01 0000
00 0000
(Main Block Top Address)
Expansion Memory
Reserved (Out-of-Range)
16
16
16
16
16
16
MBTA
: The 21 LSBits
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