pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 221

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
4.19 THE DEBUGGER INTERFACE
The Debugger Interface module links between a debugger running on a host machine and the PC87591L-N05.
The Debugger interface associates a processor number with the processor core. The number associated with the core is 0.
4.19.1 Features
4.19.2 Structure
The Debugger interface consists of a TAP, ISE Interrupt Control, Rx and Tx data links and a PC87591L-N05 reset-by-com-
mand source circuit. Figure 76 shows these functional blocks.
The TAP block has an IEEE 1149.1b 1994 standard interface to a JTAG serial bus. In addition, it uses TINT to notify the
host/debugger that a message is waiting upstream. The TAP and the JTAG form the debugging communication channel and
port for the PC87591L-N05. They operate as follows:
• Debugger communication via an IEEE 1149.1b 1994 JTAG serial bus
• Test Access Port (TAP) for JTAG serial bus
• Hardware reset signal assertion by debugger command
• Configurable ABORT event
• Interrupt signal (TINT) to the debugger indicates a waiting message
• Waiting message to on-chip processor by non-maskable ISE interrupt
• 8-word (16-byte) Rx (downstream) data link
• 8-word (16-byte) Tx (upstream) data link
• The TAP copies downstream messages (from the debugger to one of the on-chip processors) to the Rx data link, to
• A processor writes upstream messages (from an on-chip processor to its debugger) to the Tx data link for upstream
• The ISE interrupt control generates ISE interrupts to the processor in cases of ABORT or a waiting message in the
• The debugger reset circuit generates a PC87591L-N05 reset in response to a debugger reset command. This is in
be read by the relevant processor via the peripheral bus.
transmission via the JTAG serial bus.
Rx data link.
addition to the Power-Up and Hardware reset sources.
Interrupts
ISE Interrupt
ISE
Control
JTAG Serial Bus
Figure 76. Debugger Interface
(Continued)
Peripheral Bus
Tx Data
Link
TAP
221
TINT
Rx Data
Link
Debugger
Reset
To
Reset Circuit
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