pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 248

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Modules
Host Interface IRQ Control Register (HIIRQC)
The HIIRQC register controls the IRQ signals mode of operation. On reset, HIIRQC is set to 07
Location: 00 FEA2
Type:
Bit
Name
Reset
Bit
5-3
Bit
5
6
7
0
1
2
PMOCIE (PM Channel 1 Output Buffer Empty Core Interrupt Enable).
0: Interrupt signal is low (default)
1: Enables the PM Output Buffer Empty interrupt to the core ICU for PM channel 1 in PC87570 Compatible mode.
PMICIE (PM Channel 1 Input Buffer Full Core Interrupt Enable).
0: Interrupt signal is low (default)
1: Enables the PM input buffer full interrupt to the core ICU for PM channel 1 in PC87570 Compatible mode. The
Reserved.
IRQ1B (Host Interrupt Request 1 Control Bit). When the IRQ1 signal is configured for direct control by the
firmware (OBFKIE in HICTRL register is 0), IRQ1B bit is output to the IRQ1 signal. When read, IRQ1B bit
returns the current value of the IRQ1 pin. The IRQ1 signal value can be read regardless of the state of OBFKIE
bit.
IRQ12B (Host Interrupt Request 12 Control Bit). When the IRQ12 signal is configured for direct control by the
firmware (OBFMIE in HICTRL register is 0), IRQ12B bit is output to the IRQ12 signal. When read, IRQ12B bit
returns the current value of the IRQ12 pin. The IRQ12 signal value can be read regardless of the state of the
OBFMIE bit.
IRQ11B (Host Interrupt Request 11 Control Bit). When PM channel 1 is in PC87570 Compatible mode and
its host interrupt is configured for direct control by the firmware (PMHIE in HICTRL register is 0), IRQ11B bit is
output to the IRQ11 signal. When read, IRQ11B bit returns the current value of the IRQ11 signal. The IRQ11
signal value can be read regardless of the state of PMHIE bit; see Section 5.2 on page 251 for details about the
PM channel 1 interrupt scheme.
IRQM (IRQ Mode). Sets the hardware-controlled IRQ signals to work in Level or Pulse mode and defines the
pulse width in Pulse mode.
When IRQM = 000
default value is low, and a high level is set to issue an interrupt (the respective OBF is set).
When IRQM
and toggles low to issue an interrupt (i.e., when the respective output buffer register is written). The pulse width
is as follows:
Bits
5 4
0 0
0 0
0 1
0 1
1 0
1 0
Other:
R/W
The interrupt signal is active when the output buffer is empty (OBF bit is cleared in the PM channel status reg-
ister).
interrupt signal is active when the input buffer is full (IBF bit is set in the PM channel status register).
Reserved
3
0:
1:
0:
1:
0:
1:
16
Reserved
7
0
Pulse Width
Level Interrupt (default)
1-Cycle Pulse
2-Cycle Pulse
4-Cycle Pulse
8-Cycle Pulse
16-Cycle Pulse
0, the host interrupts are in Pulse mode. When IRQNPOL = 0, the signal’s default value is high
2
IRQNPOL
, the IRQ signals function in Level mode. In this mode, when IRQNPOL = 0, the signal’s
6
0
5
0
(Continued)
IRQM
Description
Description
248
4
0
3
0
IRQ11B
2
1
16
.
IRQ12B
1
1
IRQ1B
0
1
Revision 1.2