pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 291

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
5.0 Host Controller Interface Module
5.5.6
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
MSWC Control Status Register 1 (MSWCTL1)
This is a byte-wide read/write register that controls the settings associated with host wake-up and activity. The contents of
this register are preserved by V
Location: 00 FCC0
Type:
Bit
Name
Reset
Bit
0
1
2
3
MSWC Core Registers
R/W1C VHCFGA (Valid Host Configuration Address). This bit is set by a write to HCFGBAH register, as
Varies per bit
Type
R/W
RO
RO
HRSTOB (Host Reset Out Bit). Enables the PC87591L-N05 to generate a Host Soft reset via
firmware, using the KBRST pin. The pin is held low (reset is active) for as long this bit 1.
0: KBRST is not forced active (default)
1: Force KBRST active
HPWRON (Host Power On). The V
0: V
1: V
LPCRSTA (LPC Reset Active). The RESET1 input is active (low).
0: RESET1 is not active (high)
1: RESET1 is active (low)
detailed in the update sequence in “Host Configuration Address Selection” on page 284. The
firmware can clear the bit by writing 1 to it. This register is used as the address of the Configuration
registers when the PC87591L-N05 is set to operate with the internal base address. Writing 0 to this
bit is ignored. This bit can be locked and made read only by setting HCFGLK (bit 4).
0: Host Configuration Registers base address is not valid and access to this registers by the host is not
1: Host Configuration Registers base address is specified in HCFGBAH and HCFGBAL registers
16
7
0
MSWCTL1
MSWCTL2
MSWCTL3
HCFGBAL
HCFGBAH
MSIEN2
MSHES0
MSHEIE0
Reserved
Mnemonic
enabled (default)
DD
DD
is off (below V
is on (above V
CC
6
0
. Bit 0 is cleared by Warm reset; other bits are reset only on V
MSWC Control Status Register 1
MSWC Control Status Register 2
MSWC Control Status Register 3
Host Configuration Base Address Low
Host Configuration Base Address High
MSWC Interrupt Enable Register 2
MSWC Host Event Status Register 0
MSWC Host Event Interrupt Enable Register
DDON
Table 36. MSWC Core Register Map
DDON
HSECM
)
5
0
)
Register Name
(Continued)
DD
HCFGLK
power detection logic indicates that V
291
4
0
Description
VHCFGA
3
0
LPCRSTA
Varies per bit
Varies per bit
2
-
R/W1C
Type
R/W
R/W
R/W
R/W
R/W
CC
HPWRON
DD
Power-Up reset.
is on.
1
-
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HRSTOB
0
0