pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 83

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
Static Zone Configuration Register (SZCFGn)
The SZCFGn register (where n = 0, 1 or 2) controls the configuration of zone n. On reset, SZCFGn is initialized to 069F
Location: Zone 0 - 00 F984
Type:
Bit
Name
Reset
2-0
4-3
Bit
5
6
7
8
9
WAIT. This field sets the number of TIW clock cycles that extend the bus cycle. This field is ignored in read
transactions, when bit 11 (FRE) of this register is set to 1.
Bits
2 1 0 Number
0 0 0: None
0 0 1: One
0 1 0: Two
0 1 1: Three
1 0 0: Four
1 0 1: Five
1 1 0: Six
1 1 1: Seven (default)
HOLD. This field sets the number of T
(FRE) of this register is set to 1.
Bits
4 3
0 0:
0 1:
1 0:
1 1:
BRE (Burst Read Enable). This bit is ignored in read transactions, when bit 11 (FRE) of this register is set to 1.
0: Disabled (default)
1: Enabled
WBR (Wait on Burst Read). This bit determines if a wait state (TBW) is added on a burst read transaction.
0: No TBW (default)
1: TBW
BW (Bus Width). This bit sets the external bus width used for the static zone. It is initialized during reset to its
default value.
0: 8-bit bus
1: 16-bit bus (default)
Reserved.
IPST (Idle After Bus Cycle). This bit determines if an idle cycle follows the current bus cycle when the next bus
cycle is in a different zone.
0: No idle cycle inserted
1: Idle cycle inserted (default)
Zone 1 - 00 F986
Zone 2 - 00 F988
R/W
15
0
Number
None
One
Two
Three (default)
Reserved
14
0
16
16
16
13
0
12
0
FRE IPRE IPST Res
11
0
hold
10
(Continued)
1
clock cycles. This field is ignored in read transactions, when bit 11
9
1
Description
83
8
0
BW WBR BRE
7
1
6
0
5
0
4
1
HOLD
3
1
2
1
WAIT
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1
1
0
1
16
.