pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 256

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Modules
5.2.3
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
Core PM Register Map
Host Interface PM n Status Register (HIPMnST)
The HIPMnST register contains the status of the host interface PM channel buffers (DBBIN and DBBOUT). It also provides
a means for the PC87591L-N05 to send status bits to the host. This register is read by a host processor read operation from
address 66
Location: Channel 1 - 00 FEAC
Type:
Bit
Name
Reset
7-4
Bit
0
1
2
3
Core PM Registers
Channel 2 - 00 FEBE
Varies per bit
16
Type
R/W
R/W
RO
RO
RO
. HIPMnST is cleared on reset.
OBF (Output Buffer Full). The bit is set when the PM channel’s DBBOUT is written to by the core
(writing to HIPMnDO, HIPMnDOM or HIPMnDOC register). The bit is cleared by a host processor read
of the output buffer (62
IBF (Input Buffer Full). The bit is set when the PM channel’s DBBIN is written to by the host
processor (writing to either address 62
input buffer (HIPMnDI or HIPMnDIC).
F0 (Flag 0). General-purpose flag that can be set or cleared by the core firmware.
A2 (A2 Address). Indicates whether the last write operation of the host to the PMn channel was to the
data register or the Command register. Writing to this bit is ignored.
0: Last write was to the data register (pointed to by configuration register index 60
1: Last write was to the command register (pointed to by configuration register index 62
ST3-ST0 (Status). Four general-purpose flags that can be used for signaling between the host and
core. When used as an embedded controller interface channel for ACPI, a predefined meaning is
assigned to ST0, ST1 and ST2. The standard meaning is BURST, SCI event and SMI event,
respectively.
HIPMnST
HIPMnDO
HIPMnDOC
HIPMnDOM
HIPMnDI
HIPMnDIC
HIPMnCTL
HIPMnIC
HIPMnIE
7
0
Mnemonic
1. Where n stands for register 1 or 2.
1
1
1
1
1
1
1
1
1
16
16
6
0
Host Interface PM n Status
Host Interface PM n Data Out Buffer
Host Interface PM n Data Out Buffer with SCI
Host Interface PM n Data Out Buffer with SMI
Host Interface PM n Data In Buffer
Host Interface PM n Data In Buffer with SCI
Host Interface PM n Control
Host Interface PM n Interrupt Control
Host Interface PM n Interrupt Enable
ST3-ST0
16
). Writing to this bit is ignored.
5
0
Register Name
(Continued)
16
256
or address 66
4
0
Description
A2
16
3
0
). The bit is cleared by a core read of the PM
Varies per bit
F0
2
0
Type
R/W
R/W
R/W
WO
WO
WO
RO
RO
IBF
16
1
0
and 61
16
16
and 63
) (default)
OBF
0
0
Revision 1.2
16
)