pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 127

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
PS/2 Control Register (PSCON)
The PSCON register is an 8-bit read/write register. It controls the operation of the PS/2 interface by enabling it and controlling
the data transfer direction. On reset, PSCON is set to 00
Location: 00 FE84
Type:
Bit
Name
Reset
3-2
6-4
Bit
0
1
7
EN (Shift Mechanism Enable).
0: The hardware shift mechanism is disabled and the software controls and monitors the PS/2 signals using
1: The hardware shift mechanism is enabled. The enabled channels are controlled by PSOSIG, and Transmit/Re-
XMT (Transmit Enable).
0: Receive mode.
1: Causes the PS/2 interface to enter Transmit mode.
HDRV (High Drive). Defines the quasi-bidirectional buffers’ behavior on transition from low to high. HDRV
defines the period of time for which the output is pulled high with a low-impedance drive (when the PC87591L-
N05 changes the output level from low to high). This period is a function of the PC87591L-N05 clock as follows:
Bits
3 2
0 0:
0 1:
1 0:
1 1:
IDB (Input Debounce). Defines the number of PC87591L-N05 clock cycles during which the clock input is
expected to be stable before the shift mechanism identifies its new value. This protects the shift mechanism
from false edge detections. The number of PC87591L-N05 clock cycles for which the input should be stable
before an edge is detected is as follows:
Bits
6 5 4 Description
0 0 0: One cycle (default)
0 0 1: Two cycles
0 1 0: Four cycles
0 1 1: Eight cycles
1 0 0: 16 cycles
1 0 1: 32 cycles
WPUEN (Weak Pull-Up Enable).
0: The pull-up is disabled. In this state, the system must ensure that PS/2 interface signals are not floating, to en-
1: Enables the internal pull-up of the output buffer. The pull-up remains active as long as the buffer does not drive
R/W
PSOSIG and PSISIG registers (default).
ceive mode is controlled by the XMT bit.
able proper PS/2 operation (default).
the signal to low level.
WPUEN
16
Description
Disabled (default)
Low-impedance drive for one clock cycle
Low-impedance drive for two clock cycles
Low-impedance drive for three clock cycles
7
0
6
0
IDB
5
0
(Continued)
16
.
Description
127
4
0
3
0
HDRV
2
0
XMT
1
0
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EN
0
0