pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 312

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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6.0 Host-Controlled Modules and Host Interface
On host domain hardware reset in BIOS mode, the BIOS LPC Enable bit is set and the BIOS FWH Enable bit is set. The
PC87591L-N05 automatically detects the type of host boot protocol in use, via the first completed BIOS read operation after
host domain hardware reset. If the first read is an LPC memory read, the BIOS FWH Enable bit is cleared. If the first read
is an LPC-FWH read, the BIOS LPC Enable bit is cleared. Any other LPC or LPC-FWH transactions are ignored. The bits
are cleared only by the first read operation, allowing software to enable responding to these address ranges by setting the
bit. Figure 104 illustrates this behavior.
The user-defined shared memory enables sharing the memory without using it as a shared BIOS memory. The memory base
address in the host address space and the size of the shared memory are defined in the Shared Memory Base and Shared
Memory Size registers. Address bits above the block size are ignored and are internally replaced with 1s for the purpose of
address translation (e.g., for a 2 Mbyte block size, A21 through A31 are replaced with 1s).
Shared Memory Configuration Register
This register is reset on host domain hardware reset to 00
Location: Index F4
Type:
Bit
Name
Reset
Note: Only hardware-controlled transitions are shown;
Bit
0
other transitions are possible via software writes to the bits.
BIOS LPC Enable. Enables the PC87591L-N05 to respond to LPC memory accesses to the BIOS-LPC space.
The reset value of this register is defined by the SHBM configuration input. The value of this bit is updated later,
based on the detected host BIOS scheme; see “Memory Range Programing” on page 311 for details.
0: Disabled (default when SHBM disable BIOS configuration)
1: Enabled (default when SHBM enable BIOS configuration)
Host Domain
Hardware Reset
R/W
FFE0 0000
Memory Address Range
16
7
0
16
[SHBM = 0] Shared Disable BIOS
- FFFF FFFF
6
0
BIOS FWH ID
Table 51. BIOS-FWH Memory Space Definition
Figure 104. BIOS Mapping Enable Scheme
First LPC Memory Read
16
BIOS FWH Enable = 0
BIOS LPC Enable = 1
5
0
386 mode BIOS range; this is the upper 2 Mbytes of the
memory space. The PC87591L-N05 uses the first 21 ad-
dress lines and ID field to identify FWH access to the
shared memory.
16
Description
312
or 09
4
0
16
, depending on the value of the SHBM strap input.
BIOS FWH Enable = 1
BIOS LPC Enable = 1
BIOS FWH Enable = 0
BIOS LPC Enable = 0
BIOS FWH
(Continued)
Enable
Description
Strap
3
Memory
Defined
Enable
Space
User-
2
0
BIOS FWH Enable = 1
BIOS LPC Enable = 0
First LPC FWH Read
Extended
Enable
Space
BIOS
1
0
BIOS LPC
Enable
Strap
0
Revision 1.2