pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 223

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
The semaphore is implemented by DBGTXLOC register. A write operation, to PID field of this register, of a value other than
‘1111’ changes the contents of this field only when the PID field equals ‘1111’. This field returns to ‘1111’ in one of the fol-
lowing ways:
A processor can access DBGTXDi registers in Active mode only. For a processor to gain ownership of the Tx link, it must
capture the DBGTXLOC semaphore using the following sequence:
1. Verify that the value of PID in DBGTXLOC register is ‘1111’.
2. Write the processor PID code to DBGTXLOC register.
3. Read DBGTXLOC. If the PID field is equal to the value that was written, the data link is granted. If not, repeat step 1.
A processor should access DBGTXDi and DBGTXST registers only after successfully gaining ownership over the Tx link by
using the above sequence.
The TINT signal is an active-low pulse asserted by the Tx data link when ASSERT bit in DBGTINT register is written with 1.
It is de-asserted, together with the semaphore indication in Update-DR state of the TAP controller, when the current instruc-
tion loaded into TAP IR register is SCAN_TX.
Access to DBGTXLOC, DBGTXST and DBGTXDi registers should be done only while TINT is not asserted. TINT negation
can be identified by the release of PID (‘1111’).
Debugger Reset Circuit
Chip reset is asserted in the Update-DR state of the TAP controller when the current instruction is ASSERT_DBG_RST. This
triggers a Debugger reset, as described in “ASSERT_DBG_RST” on page 229. This circuit is functional in Active or Idle
modes. It is functional, while TCK is not toggling, one cycle after exit from Update-DR state.
ISE Interrupt Control
The ISE interrupt control module sends ISE interrupt requests to the processor core. It consists of the write-only DBGABORT
register, the read/write DBGISESRC register, and the DBGMASKS shift register.
The DBGISESRC register is cleared on PC87591L-N05 reset. During TAP reset, the values of these registers are main-
tained. The DBGMASKS value is modified only in Update-DR state of the TAP controller when the current instruction is
SCAN_ABORT_MASK.
The ISE interrupt control module issues an ISE interrupt request to a specific processor or multiple processors, together with
the matched bit in DBGISESRC register, according to the MESSAGE or ABORT event.
In a MESSAGE event, an ISE interrupt is requested for a specific processor according to the PID field of the SCAN_RX
instruction. The request is issued (together with DBGISESRC bit assertion) if the current instruction loaded in TAP IR is
SCAN_RX and the TAP controller is in Update-DR state (rising edge of TCK).
An ABORT event occurs when SCAN_RX is executed with a PID of all 1s (ISE and ABORT_i bits in DBGISESRC register
are asserted) or when processor bits P_i are set in DBGABORT register by one of the processors. That is, ISE and
DBGISESRC bits are asserted with the write operation itself; if DBGABORT is written with some 0 bits, the PIDs related to
these bits do not get the ISE. In an ABORT event, the assertion of each ISE interrupt and DBGISESRC bit depends on its
masking bit in DBGMASKS register.
Each ISE interrupt is cleared when ABORT_i and RX_i in DBGISESRC register are both 0. Any bit in DBGISESRC register
is cleared by writing 1 to it (writing 0 is ignored). If there is a new source activity in the same write cycle during which
DBGISESRC register of a specific processor is cleared, the ISE interrupt control asserts ISE again, together with its source
bit.
The ISE interrupt is an active-high pulse. For nested ISE sources, the ISE remains asserted, and the ISE interrupt control
module sets the new source bit to 1.
The DBGMASKS register is not available to the peripheral bus; it is accessed only from the JTAG serial bus when the
SCAN_ABORT_MASK instruction is loaded into the TAP IR.
The ISE signal, together with its source bit, should be asserted in Active or Idle modes for wake-up purposes when the
source is a debugger message or debugger abort. Other functionality should be consistent while changing modes (i.e., dur-
ing wake-up). Full functionality of this module is maintained even when TCK is not toggling.
• Write operation of ‘1111’ to PID field of DBGTXLOC register from the peripheral bus while TINT is not asserted
• Update-DR state of the TAP controller when the current instruction loaded into TAP IR register is SCAN_TX (this ac-
• On Warm or Internal reset if TINT=1 and on Power-Up reset
tion take place at the rising edge of TCK)
(Continued)
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