pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 254

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Modules
Enhanced PM Mode
Enhanced PM mode is available for both PM channels. It is enabled when EME in HIPMnCTL register is set to 1. Figure 89
shows interrupt generation in this mode.
Either IRQ, SMI or SCI interrupts may be generated under software control or by using hardware. Using hardware reduces
software overhead and simplifies procedures.
The mechanism that generates the IRQ is identical to that used in PC87570 Compatible mode. To enable identical control
of both channels, the bits that are used for channel 1 are separated from the keyboard/mouse channel’s registers; see
Figure 89 for bit usage.
IRQE in HIPMnIE register determines if an IRQ is sent from PM Channel n.
Enhanced PM mode supports direct generation of SCI and SMI on core writes to the Data output buffer and generation of
SCI on core reading of the Data Input buffer. The core decides whether to generate an interrupt and which type of interrupt
to generate by selecting the data register address in use.
When data is written to HIPMnDO register, the OBF flag in HIPMnST register is set and neither SMI nor SCI is generated.
When data is written to HIPMnDOM register, the OBF flag and the internal OBF_SMI flag are set and an SMI interrupt is
generated. The OBF_SMI flag is cleared when OBF flag is cleared. The SMI is generated as a pulse whose width is defined
by PLMM in HPIMnIC register.
The SMI interrupt is routed to the SMI pin only if both HSMIE and SMIE bits in HIPMnIE register are set. When SMIE is set
and HSMIE is cleared, SMIB in HIPMnIC register is used as the PMnSMI signal value. When SMIE is cleared, the PMnSMI
signal is inactive (high).
When data is written to HIPMnDOC register, the OBF flag and OBF_SCI internal flag are set and an SCI interrupt is gener-
ated. OBF_SCI is cleared when OBF is cleared. The SCI is generated as a pulse whose width is defined by PLMS in
HPIMnCTL register.
HIPMnDO (write)
HIPMnDOM (write)
HIPMnDOC (write)
SCIIS bit (HPMnIC)
HIPMnDIC (read)
HIPMnDI (read)
(HIPMnST)
OBF bit
(write 1)
IRQB bit (HIPMnIC)
IRQM field (HIIRQC)
Hardware
Interrupt
IRQB bit (HIPMnIC)
set OBF_no_int
set OBF_SCI
set OBF_SMI
clear IBF bit (HIPMnST)
(write)
set IBF_SCI
Figure 89. IRQ, SCI and SMI Control, Enhanced PM Mode
(read)
IRQNPOL bit (HIIRQC)
IRQB bit (HIPMnIC)
SCIB bit (HIPMnIC)
PLMS field (HIPMnCTL)
SMIB bit (HIPMnIC)
PLMM field (HIPMnIC)
1
0
Pulse Shape
Pulse Shape
(Continued)
HIRQE bit (HIPMnIE)
254
HSMIE bit (HIPMnIE)
HSCIE bit (HIPMnIE)
1
0
1
0
1
0
SCIB bit (HIPMnIC) (read)
SMIE bit (HIPMnIE)
IRQE bit (HIPMnIE)
SCIE bit
(HIPMnIE)
SMIB bit (HIPMnIC)
PMnECSCI of
other channel
(read)
SCIPOL bit (HIPMnCTL)
1
SMIPOL bit (HIPMnIC)
1
0
0
SuperI/O
Routing
(Part of
Module)
PMnECSCI
Polarity
Config
IRQ
and
Gathering
Source
SMI
Serializer
PMnSMI
IRQ
ECSCI
Revision 1.2