pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 17

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
Table of Contents
6.0
Host-Controlled Modules and Host Interface
6.1
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
DEVICE ARCHITECTURE AND CONFIGURATION .............................................................. 297
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
Wake-Up Output Events ............................................................................................ 283
Other MSWC Controlled Elements ............................................................................ 284
MSWC Host Registers ............................................................................................... 285
MSWC Core Registers .............................................................................................. 291
Usage Hints ............................................................................................................... 296
Configuration Structure and Access .......................................................................... 297
Standard Configuration Registers ............................................................................. 302
Default Configuration Setup ...................................................................................... 303
Address Decoding ..................................................................................................... 303
Interrupt Serializer ..................................................................................................... 304
Protection .................................................................................................................. 304
LPC Interface ............................................................................................................. 304
SuperI/O Configuration Registers .............................................................................. 306
(Continued)
Host Configuration Address Selection .................................................................. 284
Host Keyboard Fast Reset ................................................................................... 284
GA20 Pin Functionality ......................................................................................... 285
MSWC Host Register Map ................................................................................... 285
Wake-Up Event Status Register 0 (WK_STS0) ................................................... 286
Wake-Up Events Enable Register (WK_EN0) ...................................................... 286
Wake-Up Configuration Register (WK_CFG) ....................................................... 287
Wake-Up Signals Value Register (WK_SIGV) ..................................................... 288
Wake-Up ACPI State Register (WK_STATE) ...................................................... 288
Wake-Up Event Routing to SMI Enable Register 0 (WK_SMIEN0) ..................... 289
Wake-Up Event Routing to IRQ Enable Register 0 (WK_IRQEN0) ..................... 290
MSWC Control Status Register 1 (MSWCTL1) .................................................... 291
MSWC Control Status Register 2 (MSWCTL2) .................................................... 292
MSWC Control Status Register 3 (MSWCTL3) .................................................... 293
Host Configuration Base Address Low (HCFGBAL) ............................................ 293
Host Configuration Base Address High (HCFGBAH) ........................................... 293
MSWC Interrupt Enable Register 2 (MSIEN2) ..................................................... 294
MSWC Host Event Status Register 0 (MSHES0) ................................................. 294
MSWC Host Event Interrupt Enable Register (MSHEIE0) ................................... 295
PWUREQ Output Connection .............................................................................. 296
RESET2 Events ................................................................................................... 296
The Index-Data Register Pair ............................................................................... 297
Banked Logical Device Registers Structure ......................................................... 298
Standard Logical Device Configuration Register Definitions ................................ 299
SuperI/O Control and Configuration Registers ..................................................... 302
Logical Device Control and Configuration Registers ............................................ 302
Control .................................................................................................................. 302
Standard Configuration ........................................................................................ 303
Special Configuration ........................................................................................... 303
LPC Transactions Supported ............................................................................... 304
Core Interrupt ....................................................................................................... 305
CLKRUN Functionality ......................................................................................... 305
LPCPD Functionality ............................................................................................ 305
SuperI/O ID Register (SID) ................................................................................... 306
17
www.national.com