pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 237

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
4.20.5 Freezing Events
The PC87591L-N05 can prevent real-time events from interfering with the operation of the ADB monitor and changing the
status of the PC87591L-N05. This is done by disabling maskable interrupts and setting FREEZE bit; the FREEZE bit freezes
the watchdog timer and disables destructive read operations.
Disabling Maskable Interrupts
Clearing the core I or E bits in PSR register disables the maskable interrupts. The I bit is cleared automatically whenever a
trap or interrupt occurs and after reset.
Freezing the Watchdog Timer
To freeze the watchdog timer, FREEZE bit in DBGCFG register must be set to 1 on entering a TMON routine (the bit must
be cleared before returning to the application). Setting FREEZE bit prevents the watchdog from generating the reset that
occurs if watchdog is not cleared in time (see Section 4.10 on page 160). The watchdog timer keeps its value while it is fro-
zen and resumes counting after FREEZE is cleared.
If an application fails to touch the watchdog in time and a reset event is generated before or while FREEZE bit is set, the
PC87591L-N05 receives the reset.
Disabling Additional Modules
The two MFT16, the two USARTs and the four ACB modules may be frozen by the FREEZE bit. Freezing is enabled when
the respective bit in DBGFRZEN register is set; the bits can be set to meet specific needs of different applications.
Disabling Destructive Reads
When FREEZE in DBGCFG register is set (1), destructive reads do not change the system state (i.e., they return the read
data but do not clear or set bits or send signals). This allows the debugger to present the values of these bits. NMISTAT is
an exception to this rule and is not affected by FREEZE. Core accesses to Host domain registers (using the “Core Access
to Host Controlled Modules”) may also be destructive but are not affected by FREEZE. Note that host operations continue
without any FREEZE bit impact.
4.20.6 Monitoring Activity During Development
In DEV environment, information is available for monitoring on-chip activities and implementing debug features in the devel-
opment system.
Bus Status Signals
The Bus Status signals (BST2-0) indicate if a transaction on the core bus was issued and, if so, the type of transaction.
The BST2-0 signals reflect activity on the core bus. For word accesses involving 8-bit expansion memory, the core bus cycle
triggers two external bus cycles. The first external bus cycle is flagged as a T1 cycle of the core bus. The second is not
flagged as a T1 cycle, i.e., BST2-0 is 000. See Table 31.
BST
000
001
010
011
100
101
110
111
Table 31. Core Bus Transaction Encoding
Not a T1 cycle, except when the core waits for an
interrupt following WAIT instruction execution
Core waits for an interrupt following WAIT
instruction execution
T1 of an interrupt acknowledge bus cycle
T1 of a data transfer of a non-core bus master
T1 of a sequential instruction fetch
T1 of a non-sequential instruction fetch
T1 of a core data transfer
T1 of an exception data transfer
(Continued)
Core Bus Transaction Type
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