pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 266

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
5.0 Host Controller Interface Module
5.3.5
The host read/write protection is software controlled via a set of registers accessible to the host. The protection granularity
is per block. Each of the 32 software-controlled protection blocks is 64 Kbytes; the block’s read protection and write protec-
tion flags may be set independently. A Lock Protect flag may be set to prevent future changes to the read and write protection
bits. Once locked, the lock bit and the read/write enable bits may be changed only after Host Domain Hardware reset.
The core can override the host settings and prevent host access to certain areas of the shared memory. The override may
be set independently for read and write. In the first 128 Kbytes of address space, each core-controlled block is 8 Kbytes. For
the rest of the memory space the blocks are 64 Kbytes each.
The default value of the protection registers is set according to the properties of the block. There are three types of blocks:
Core on-chip peripherals and RAM are never accessible to the host (for both read and write). The range from MBTA to
0 FFFF
Core Boot Block
This block is not accessible by the host and (for either read or write). The core boot block starts at address 0 0000
ends as defined in the Core Boot Block field of the PTWRL register (4 Kbytes). The core boot block access protection set-
tings (in SMCOxP0-2 registers) may not be changed, and the respective protection bits are read only.
Host Boot Block
By default, this block may be read by the host. Host writes to this block are always disabled. The host boot block size is
64 Kbytes and is available when the Host Boot Block bit in PTWRL register is 0. The Host boot block is located at the upper
64 Kbytes of the core memory space (1F 0000
aries and on the MBTA value forced to 0 0000
between the host boot block and the core boot block, access protection settings of the core boot block are used. The host
boot block access protection settings may not be changed, and the respective protection bits are read only.
Other Blocks
By default, all other blocks are read and write protected. The core may enable host read and/or write access to these blocks.
Setting the Host Access Protection Flags
There are two sets of host access protection flags, as shown in Figure 93:
Host-Controlled Host Access Protection Flags. For each of the 32 protection blocks there is a set of three bits (flags):
Read Protect, Write Protect and Lock Protect. The 32 sets of flags are accessible via two registers, Shared Memory Host
Access Protect Register 1 and 2 (SMHAP1-2), using an indexing scheme.
The Host Block index may be calculated using the following equation:
See Section 5.3.2 on page 262 for the definitions of the host address translation.
Core-Controlled Host Access Protection Flags. For core-controlled host access protection there is a read protect and write
protect bit for each block The core block number are parallel to the host blocks for blocks 2-31. The core-controlled host access
protection has a finer granularity for the first two host blocks, which are split into 16 core blocks, indicated as LA0 - LA15.
The block number may be calculated using the following equation:
• Core Boot Block: Read, Erase and Program protected from the host (in PC87591L-N05 the core boot block is imple-
• Host Boot Block: Open for Read by the host; Erase and Program protected from the host.
• Other Blocks:
• Host-controlled host access protection flags
• Core-controlled host access protection flags
• To change a flag setting, write the new flag setting, together with the required index field (i.e., Host Access Protection
• To read the values of the flags:
Index) and a cleared Index Write bit, to the appropriate register (SMHAP1 or SMHAP2).
1. Read the value of the register and save the index field.
2. Write the index of the register’s flag (i.e., write the index with a 1 in the Index Write bit).
3. Read the settings of the register’s flag.
4. Restore the index field by writing back the value of the index field stored in step 1.
Host_Block_Index = CR_Space_Address[20-0] / 64K or
Host_Block_Index = (21 least significant bits)(SM_Host_Address + MBTA) / 64K
Core_Block_Number = (CR_Space_Address < 128K) ?
16
Host Access Protection
should be protected from host access using the core-controlled protection registers.
mented in ROM).
Open for Read, Erase and Program by the host.
CR_Space_Address[20-0] / 64K : CR_Space_Address[20-0] / 8K
16
16
(the latter by Force MBTA Zero bit in PTWRL register). In case of an overlap
to 1F FFFF
(Continued)
266
16
), based on both the core address folding at 2 Mbyte bound-
Revision 1.2
16
and