pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 261

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
5.0 Host Controller Interface Modules
Host Interface PM n Interrupt Enable Register (HIPMnIE)
The HIPMnIE register controls the PM n interrupt signals that enable SMI, SCI and IRQ interrupts. HIPMnIE is cleared on reset.
Location: Channel 1 - 00 FEBC
Type:
Bit
Name
Reset
7-6
Bit
0
1
2
3
4
5
IRQE (IRQ Enable).
0: PMnIRQ signal assumes its default value (low) and no interrupts are issued (default)
1: Enables PM generation of IRQ events
SCIE (SCI Enable).
0: PMnSCI signal assumes its default value (high) and no interrupts are issued (default)
1: Enables PM generation of SCI events
SMIE (SMI Enable).
0: PMnSMI signal assumes its default value (high) and no interrupts are issued (default)
1: Enables the generation of SMI events by this module
HIRQE (Hardware IRQ Enable). Works only in Enhanced PM mode.
0: IRQB bit of HIPMnIC register controls the value of the IRQ (default)
1: Enables the generation of IRQ events by hardware control based on the status of the OBF flag
HSCIE (Hardware SCI Enable). Works only in Enhanced PM mode.
0: SCIB bit in HIPMnIC register controls the value of the SCI (default)
1: Enables the generation of SCI events by hardware control based on the status of the OBF and IBF flags
HSMIE (Hardware SMI Enable). Works only in Enhanced PM mode.
0: SMIB bit in HIPMnIC register controls the value of the SMI (default)
1: Enables the generation of SMI events by hardware control based on the status of the OBF flag
Reserved.
Channel 2 - 00 FECE
R/W
7
0
Reserved
16
16
6
0
HSMIE
5
0
(Continued)
HSCIE
Description
261
4
0
HIRQE
3
0
SMIE
2
0
SCIE
1
0
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IRQE
0
0