pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 185

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
The ACCESS.bus master generates Start and Stop Conditions (control codes). After a Start Condition is generated, the bus
is considered busy. It retains this status for a given amount of time after a Stop Condition is generated. A high-to-low tran-
sition of the data line (SDAn) while the clock (SCLn) is high indicates a Start Condition. A low-to-high transition of the SDAn
line while the SCLn is high indicates a Stop Condition (Figure 67).
In addition to the first Start Condition, a Repeated Start Condition can be generated in the middle of a transaction. This allows
either another device to be accessed or a change in the direction of the data transfer.
Acknowledge Cycle
The Acknowledge cycle consists of two signals:
The master generates the Acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases
the SDAn line (permitting it to go high) to allow the receiver to send the Acknowledge signal.The receiver pulls down the
SDAn line during the Acknowledge clock pulse, thus signalling that it has correctly received the last data byte and is ready
to receive the next byte. Figure 69 shows the Acknowledge cycle.
“Acknowledge After Every Byte” Rule
The master generates an Acknowledge clock pulse after each byte transfer. The receiver sends an Acknowledge signal after
every byte is received.
• Acknowledge Clock pulse is sent by the master with each byte transferred
• Acknowledge signal is sent by the receiving device (see Figure 68)
Data Output
Receiver
Transmitter
Data Output
SDAn
SCLn
SCLn
Start
Condition
S
Start
Condition
SDAn
SCLn
S
MSB
1
Figure 69. ACCESS.bus Acknowledge Cycle
Figure 68. ACCESS.bus Data Transaction
2 3 - 6
Figure 67. Start and Stop Conditions
1
Start
Condition
S
Byte Complete
Interrupt within
2 3 - 6
(Continued)
7
Receiver
8
7
ACK
185
9
8
Acknowledge Signal
from Receiver
9
1
Clock Line Held
Low by Receiver
while Interrupt
is Serviced
2
3 - 8
Stop
Condition
Transmitter Stays Off the
Bus During the
Acknowledge Clock
Acknowledge
Signal from Receiver
P
ACK
9
Stop
Condition
P
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