pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 95
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pc87591l-n05
Manufacturer Part Number
pc87591l-n05
Description
Lpc Mobile Embedded Controller
Manufacturer
National Semiconductor Corporation
Datasheet
1.PC87591L-N05.pdf
(401 pages)
- Current page: 95 of 401
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Revision 1.2
4.0 Embedded Controller Modules
4.2.9
• Do not write to ADCAn, ADCBn or BLTCn and do not change the value of TCS, IND, DIR, OT, ADA, INCA, ADB and
• The ADRAn, ADRBn and BLTRn registers store transfer parameters (source address, destination address and block
• The TCS bit in DMACNTLn register is programed according to the bus width of the devices. It determines how many
• The DMAC does not support non-aligned transfers. The values written to ADCAn, ADRAn, ADCBn and ADRBn must
INCB fields of DMACNTLn register while the associated channel is active (CHAC bit in DMASTATn register is 1).
When initializing these registers, write to BLTCn register last, since writing to BLTCn register activates the channel
immediately (if CHEN bit in DMACNTLn register is set to 1).
length) for the next data block to be transferred, for either Auto-Initialize or Double-Buffer modes of operation. When
initializing these registers, write the BLTRn register last, since this validates the next block’s parameters (VLD bit in
DMASTATn register is set to 1).
bytes are transferred in each DMA bus cycle.
be multiples of the Transfer Cycle Size (as defined by TCS bit in DMACNTLn register).
Usage Hints
(Continued)
95
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