pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 25

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
1.0 Introduction
ules, and four power modes. These power modes include:
1.2.3
The PC87591L-N05 can operate in one of the following three environments:
1.3
The PC87591L-N05 consists of several main components, divided into three groups:
The descriptions below detail the functions of the various blocks shown in Figure 2.
• Active Mode - Full functionality
• Active Mode Executing WAIT Instruction - Core execution and associated operations (such as memory access) are suspended
• Idle - Main clock is stopped, but the device can be woken up by internal or external events. The system tick timer is
• Power Off - V
• Internal ROM Enabled (IRE). Used while the PC87591L-N05 operates in the production system and executes the
• On-Board Development (OBD). Used to debug the PC87591L-N05 code while it is mounted on its final production
• Development (DEV). Used in Application Development Boards (ADB) or In System Emulators (ISE). In this environ-
• Core Domain
• Host Domain
• Host-Controller Interface
still operational and can be used to periodically wake up the device.
state of some memory and configuration elements.
application. The external ROM is the main source of code for the device.
board. All pins have their IRE functionality. Interface to a debugger (running on the host) is through the JTAG-based
debugger interface. OBD environment is binary and cycle-by-cycle compatible with IRE environment.
ment, the external ROM is replaced with off-chip SRAM memory to allow flexible and fast development of application
code. Some pins are allocated to development system use, and the GPIO functions associated with them are repli-
cated using off-chip logic as part of the ADB system. DEV environment is binary and cycle-by-cycle compatible with
OBD and IRE environments.
— CR16B core processing unit
— Bus Interface Unit and Memory Controller (BIU)
— RAM and ROM memory
— Core peripherals
— Host-Controlled functions
— Host Interface
INTERNAL ARCHITECTURE
Operating Environments
Host
Controlled
Functions
CC
Internal Bus
is absent and only backup battery is available to supply the Real Time Clock (RTC) and retain the
(Continued)
LPC
KBC + PM
I/F
Host I/F
LPC Bus I/F
Serial
IRQ
32.768 KHz
Figure 2. PC87591L-N05 Functional Block Diagram
MSWC
RTC
SMI
CR Access
HFCG
Bridge
Core Bus
I/F Functions
PMC
Reset &
Config
Peripheral Bus
CLK
ICU
Shared mem.
+ Security
MIWU
25
CR16B Core
KBSCAN +
ACM
Debugger
Adapter
JTAG
Bus
I/F
GPIO
Processing
PS/2
RAM
I/F
Unit
Memory
ACB
(X4)
MFT16
(X2)
Timer +
WDG
ROM
Peripherals
PWM
ADC
DAC
DMA
USART
(X2)
BIU
Memory + I/O
External
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