pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 187

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
Sending the Address Byte
Once the PC87591L-N05 is the active master of the ACCESS.bus (MASTER in ACBnST register is set), it can send the ad-
dress on the bus. The address sent should not be any of the following:
To send the address byte, use the following sequence:
1. For a receive transaction where the software requires only one byte of data, the software should set ACK in ACBnCTL1
2. Write the address byte (7-bit target device address) and the direction bit to ACBnSDA register. This causes the module to
3. If STASTRE in ACBnCTL1 register is set and the transaction was successfully completed (i.e., both BER and NEGACK
4. If the requested direction is transmit and the start transaction was completed successfully (i.e., neither NEGACK nor BER
5. If the requested direction is receive, the start transaction was completed successfully and STASTRE in ACBnCTL1 reg-
6. Check that both BER and NEGACK in ACBnST register are cleared. If either INTEN in ACBnCTL1 register or DMAEN
Master Transmit
After becoming the bus master, the device can start transmitting data on the ACCESS.bus.
In interrupt or polling operation, to transmit a byte, the software should:
1. Check that BER and NEGACK bits in ACBnST register are cleared and SDAST bit is set. In addition, if STASTRE bit in
2. Write the data byte to be transmitted to ACBnSDA register.
In DMA operation:
When NEGACK or BER in the ACBnST register is set, an interrupt is generated and the ACB stops sending DMA re-
quests.When the slave responds with a negative acknowledge, NEGACK in ACBnST register is set and SDAST in ACBnST
register remains cleared. In this case, if INTEN bit in ACBnCTL1 register or DMAEN bit in ACBCTL1 register is set, an in-
terrupt is sent to the core.
Master Receive
After becoming the bus master, the device can start receiving data on the ACCESS.bus.
In interrupt or polling operation, to receive a byte, the software should:
1. Check that SDAST bit in ACBnST register is set and BER bit is cleared. In addition, if STASTRE bit in ACBnCTL1 register
2. If the next byte is the last byte that should be read, set ACK bit in ACBnCTL1 register to 1. This causes a negative ac-
3. Read the data byte from ACBnSDA register.
In DMA operation:
Before receiving the last byte of data, set ACK in the ACBnCTL1 register. This should be done by programing the DMA to
interrupt the CPU one byte before the end of the transmission, and letting the software set ACK.
• The PC87591L-N05’s own address, as defined by ADDR in ACBnADDR register, if SAEN in ACBnADDR is set.
• The PC87591L-N05’s own address, as defined by ADDR in ACBnADDR2, if SAEN in ACBnADDR2 is set.
• The global call address, if GCMATCH in ACBnCST register is set.
• The ARP address, if ARPMATCH in ACBnST register is set.
• If DMAEN in the ACBnCTL1 register was set before the start transaction, a DMA request is generated automatically
• The DMA request becomes active after the module receives a byte of data. If an error occurs during the transaction
register. If only an address needs to be sent (e.g., for quick read/write protocols) or if the device requires stall for some
other reason, set STASTRE in ACBnCTL1 register to 1.
generate a transaction. At the end of this transaction, the acknowledge bit received is copied to NEGACK in ACBnST reg-
ister. During the transaction, the SDAn and SCLn lines are continuously checked for conflict with other devices. If a conflict
is detected, the transaction is aborted, BER in ACBnST register is set and MASTER in ACBnST register is cleared.
in ACBnST register are cleared), STASTR in ACBnST register is set. In this case, the ACB stalls any further AC-
CESS.bus operations (i.e., holds SCLn low). If INTEN in ACBnCTL1 register is set, it also sends an interrupt to the core.
in ACBnST register is set and no other master has accessed the device), SDAST in ACBnST register is set to indicate
that the module awaits attention.
ister is cleared, the module starts receiving the first byte automatically.
in the ACBnCTL1 register is set, an interrupt is generated when either BER or NEGACK is set.
ACBnCTL1 register is set, make sure that STASTR bit in ACBnST register is cleared.
at the end of the address transaction and after each following transaction, unless for some reason (e.g., ACBnCST,
MATCH or BER were set) an interrupt was generated.
is set, make sure that STASTR in ACBnST register is cleared.
knowledge to be sent.
(e.g., NMATCH in the ACBnCST register or BER in the ACBnST register is set), an interrupt is generated and DMA
operation is stalled.
(Continued)
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