pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 320

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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Host-Controlled Modules and Host Interface
Connections
Connect the clock to the 32KCLKIN pin, leaving the oscillator output, 32KX2, unconnected.
Signal Parameters
The signal levels should conform to the voltage level requirements for 32KCLKIN/32KX1, stated in Chapter 7 on page 334.
The signal should have a duty cycle of approximately 50%. To oscillate during power-down, it should be sourced from a
battery-backed source. This guarantees that the RTC delivers updated time/calendar information.
6.2.5
The timing generation function divides the 32.768 KHz clock by 2
seconds counter. This is performed by a divider chain composed of 15 divide-by-two latches, as shown in Figure 107.
Bits 6-4 (DV2-0) of CRA register control the following functions:
The divider chain can be activated by setting normal operational mode (bits 6-4 of CRA = 010
500 ms after divider chain activation.
Bits 3-0 of CRA register select one the of 15 taps from the divider chain to be used as a periodic interrupt. The periodic flag
becomes active after half of the programed period has elapsed, following divider chain activation.
See “RTC Control Register A (CRA)” on page 329 for more details.
6.2.6
Data Format
Time is kept in BCD or binary format, as determined by bit 2 (DM) of Control Register B (CRB), and in either 12 or 24-hour
format, as determined by bit 1 of this register.
Note: When changing the above formats, re-initialize all the time registers.
Daylight Saving
Daylight saving time exceptions are handled automatically, as described in “RTC Control Register B (CRB)” in
Section 6.2.15 on page 325.
Leap Years
Leap year exceptions are handled automatically by the internal calendar function. Every four years, February is extended to
29 days. Year 2000 is a leap year.
• Normal operation of the divider chain (counting)
• Divider chain reset to 0
• Oscillator activity when only V
Timing Generation
Timekeeping
32KCLKIN
32KX1 /
BAT
power is present (backup state).
32.768 KHz
Figure 107. Divider Chain Control
1
2
32KX2
2
2
CRA Register
Divider Chain
DV2 DV1 DV0
3
6
2
5
To other
modules
Reset
320
4
(Continued)
15
13
2
to derive a 1 Hz signal, which serves as the input for the
14
2
15
2
1 Hz
Enable
Oscillator
2
). The first update occurs
Revision 1.2