pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 395

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
C. Booter Program
Header 2 includes the following:
• ROM Size: (1 word at offset 0)
• Start 1: (1 word at offset 2)
• Checksum: (1 byte at offset 4)
This is the length, in bytes, of the area for which checksum is performed.
The firmware (EC BIOS) entry point address. This is the PC value; thus its value is the address divided by 2.
The checksum result of Header 2.
To generate the value of this field, first calculate the checksum starting at offset 00 of Header 2, up to the offset of the
“last_ROM_byte”, not including offset 04 (Checksum), byte per byte; then calculate the 1-byte 2’s complement of this
number and store it in offset 04 (Checksum). The offset of the “last_ROM_byte” is the value of the ROM Size minus 1.
5-3 HFCG Clock Frequency. Determines the clock frequency that is set before performing the checksum.
7-6 Reserved
Bit
1
2
USART Configuration.
0: Do not configure USART module for debug before booting
1: Configure USART module for debug before booting
Force Recovery Mode.
0: If the header is valid, perform boot normally
1: Enter recovery mode in all cases
Bits
5 4 3
0 0 0:
0 0 1:
0 1 0:
0 1 1:
Other:
Frequency
4 MHz
8 MHz
16 MHz
20 MHz
Reserved
(Continued)
Offset
00-01
02-03
07
04
05
06
08
09
10
11
13
15
16
20
18
21
Length
1
1
1
1
2
1
2
2
2
1
1
1
2
2
1
3
XOR Checksum Res.
Description
395
Forced Update 3
Forced Update 1
Forced Update 2
Protection Word
MCFG_DAT
ZONE0CFG
ZONE1CFG
ZONE2CFG
Checksum
Flash Size
ROM Size
Reserved
Reserved
Start 1
PNMR
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