pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 158

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Interrupt Control Register (UnICTRL)
This byte-wide register contains the interrupt enable bits and the interrupt status flags. The register is set to 01
Location: USART1 - 00 FD24
Type:
Bit
Name
Reset
4-2
Bit
0
1
5
6
7
USART2 - 00 FC24
Varies per bit
Type
R/W
R/W
R/W
RO
RO
EEI
TBE. The bit is set by the hardware when the USART transfers data from UnTBUF register to TSFT
register for transmission. It is automatically cleared on the next write to UnTBUF register. The bit is set
on reset.
0: Transmit buffer not empty
1: Transmit buffer empty (default)
RBF. The bit is set by the hardware when the USART has received a complete data frame and
transferred the data from RSFT register to UnRBUF register. The bit is automatically cleared when
RBUF register is read.
0: Receive buffer not full. New data has not been transferred to RBUF since the last time it was read (default)
1: Receive buffer full. RBUF contains new data since the last time it was read
Reserved.
ETI. A TX interrupt is generated when the TBE flag is set.
0: Disable transmitter interrupt (default)
1: Enable transmitter interrupt
ERI. An RX interrupt is generated when the RBF flag is set.
0: Disable receiver interrupt (default)
1: Enable receiver interrupt
EEI. An RX interrupt is generated when the ERR flag is set, indicating that a receive error has
occurred.
0: Disable receive error interrupt (default)
1: Enable receive error interrupt
7
0
16
16
ERI
6
0
ETI
5
0
(Continued)
158
4
0
Description
Reserved
3
0
2
0
RBF
1
0
16
on reset.
TBE
0
1
Revision 1.2