pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 40

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

www.national.com
2.0 Signal/Pin Description and Configuration
2.2.5
RD
SEL0
SEL12_
SEL2
SELIO
WR1
WR0
BE1-0
BRKL_RSTO 76
BST2-0
CBRD
PFS
PLI
TCK
TDI
TDO
TINT
TMS
Signal
Signal
Development System Support
150
173
174
152
48
151
121,129
69, 63-62
120
70
75
106
108
107
105
109
Pin(s)
LQFP
Pin(s)
LQFP
A9
A4
A3
D8
R3
C9
E12, D15
P10
M9, N7, R7
F14
N10
R9
J15
H12
J13
K14
J14
Ball(s)
FBGA
Ball(s)
FBGA
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
IN
Buffer
Buffer
Type
IN
O
O
O
O
O
O
OD
Type
T
IN
IN
O
O
O
O
O
/O
1/2
1/2
1/2
1/2
1/2
1/2
TS
1/2
1/2
1/2
1/2
1/2
T
T
2
1/2
40
Power
Power
Well
V
V
V
V
V
V
V
V
V
V
V
Well
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
(Continued)
Byte Enable bits 1 and 0 on monitor bus cycles.
Break Line and Reset Out. When the Core bus is
active, the pin is used as a BRKL input. It indicates
to the core that a breakpoint is needed when the
currently fetched instruction goes into execution.
When the Core bus is not active, the signal is used
as a RSTO output. It indicates to the system that an
internal reset to the core and its peripherals
occurred.
Bus Status bits 2-0 on monitor bus cycles. In DEV
environment, these pins allow monitoring of the
external bus cycles. When OBR bit in BCFG register
is set, the internal bus cycles are also visible on the
external bus. See also Table 31 on page 237.
Core Bus Read Status on monitor bus cycles.
Available in all modes. See Section 4.1.9 on
page 80.
Pipe Flow Status.
Pipe Long Instruction.
JTAG Test Clock.
JTAG Test Data In.
JTAG Test Data Out.
JTAG Test Interrupt.
JTAG Test Mode Select.
Read Control. Core external read strobe. Can be
used as output enable for external memory of I/O
devices.
Zone Select 0. Chip-select signal for external
memory devices mapped to zone 0.
Zone Select 1 and 2. Chip-select signal for external
memory devices mapped to zones 1 and 2. Zone
Select 1 is available in DEV environment for off-chip
emulation of the on-chip ROM. In IRE and OBD
environments, SEL2 output is used for Zone Select
2 when zone 2 is enabled.
I/O Zone Select. Chip-select signal for external I/O
devices mapped to this zone. Can be used for
mapping off-chip I/O expansion devices to the core
address space.
Write Control 1 and 0. Indicates writes to bytes 1
and 0, respectively, of the BIU data bus.
Description
Description
Revision 1.2