HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 1020

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 21 Flash Memory (0.18-μm F-ZTAT Version)
21.9
1. Download time of on-chip program
2. Write to flash-memory related registers by DMAC
3. Compatibility with programming/erasing program of conventional F-ZTAT H8 microcomputer
4. Monitoring runaway by WDT
5. Notes on supplying power
6. User branch processing intervals
Table 21.15 User Branch Processing Start Intervals
Programming operation
Erasing operation
Rev.7.00 Mar. 18, 2009 page 952 of 1136
REJ09B0109-0700
The programming program that includes the initialization routine and the erasing program that
includes the initialization routine are each 4 kbytes or less. Accordingly, when the CPU clock
frequency is 35 MHz, the download for each program takes approximately 60 μs at maximum.
While an instruction in on-chip RAM is being executed, the DMAC can write to the SCO bit
in FCCS that is used for a download request or FMATS that is used for MAT switching. Make
sure that these registers are not accidentally written to, otherwise an on-chip program may be
downloaded and damage RAM or a MAT switchover may occur and the CPU get out of
control. Do not use DMAC to program FLASH related registers.
A programming/erasing program for flash memory used in the conventional F-ZTAT H8
microcomputer which does not support download of the on-chip program by a SCO transfer
request cannot run in this LSI. Be sure to download the on-chip program to execute
programming/erasing of flash memory in this LSI.
Unlike the conventional F-ZTAT H8 microcomputer, no countermeasures are available for a
runaway by WDT during programming/erasing by the downloaded on-chip program. Prepare
countermeasures (e.g. use of the periodic timer interrupts) for WDT while taking the
programming/erasing time into consideration as required.
When the power is supplied, the reset signal must be a low level and the external-input clock
must be supplied.
The user branch processing interval differs for programming and erasing operations. Table
21.15 shows the maximum start intervals when the CPU clock frequency is 35 MHz.
Usage Notes
Maximum Interval
1 ms
30 ms