HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 331

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

• Normal space access after a continuous synchronous DRAM space write access
Table 6.11 shows whether there is an idle cycle insertion or not in the case of mixed accesses to
normal space and DRAM space/continuous synchronous DRAM space.
Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
If a normal space read cycle occurs after a continuous synchronous DRAM space write access
while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The
number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC.
It is not in accordance with the DRMI bit in DRACCR.
Figure 6.80 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
DQMU, DQML
Precharge-sel
Address bus
HWR, LWR
Data bus
CKE
CAS
RAS
WE
RD
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)
φ
PALL ACTV
address
Column
T
Continuous synchronous
DRAM space write
p
address
address
Row
Row
T
r
NOP WRIT
T
c1
address
Column
T
c2
Idle cycle
External address space read
T
i
External address
External address
Rev.7.00 Mar. 18, 2009 page 263 of 1136
T
1
High
NOP
T
2
Section 6 Bus Controller (BSC)
T
3
READ
Synchronous
DRAM space read
T
Column address 2
c1
REJ09B0109-0700
T
Cl
NOP
T
c2