HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 31

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8.5
8.6
Section 9 Data Transfer Controller (DTC) ........................................................425
9.1
9.2
9.3
9.4
9.5
9.6
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10 EXDMAC Bus Cycles (Single Address Mode) .................................................... 400
8.4.11 Examples of Operation Timing in Each Mode...................................................... 405
8.4.12 Ending DMA Transfer .......................................................................................... 418
8.4.13 Relationship between EXDMAC and Other Bus Masters .................................... 419
Interrupt Sources ................................................................................................................ 420
Usage Notes ....................................................................................................................... 422
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
Features .............................................................................................................................. 425
Register Descriptions ......................................................................................................... 427
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
Activation Sources ............................................................................................................. 432
Location of Register Information and DTC Vector Table ................................................. 433
Operation............................................................................................................................ 437
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
Procedures for Using DTC................................................................................................. 447
9.6.1
9.6.2
Repeat Area Function ........................................................................................... 383
Registers during DMA Transfer Operation........................................................... 385
Channel Priority Order.......................................................................................... 390
EXDMAC Bus Cycles (Dual Address Mode)....................................................... 393
EXDMAC Register Access during Operation ...................................................... 422
Module Stop State................................................................................................. 422
EDREQ Pin Falling Edge Activation.................................................................... 422
Activation Source Acceptance .............................................................................. 423
Enabling Interrupt Requests when IRF = 1 in EDMDR ....................................... 423
ETEND Pin and CBR Refresh Cycle.................................................................... 423
DTC Mode Register A (MRA) ............................................................................. 427
DTC Mode Register B (MRB).............................................................................. 429
DTC Source Address Register (SAR)................................................................... 429
DTC Destination Address Register (DAR)........................................................... 429
DTC Transfer Count Register A (CRA) ............................................................... 430
DTC Transfer Count Register B (CRB)................................................................ 430
DTC Enable Registers A to H (DTCERA to DTCERH) ...................................... 430
DTC Vector Register (DTVECR)......................................................................... 431
Normal Mode........................................................................................................ 440
Repeat Mode ......................................................................................................... 441
Block Transfer Mode ............................................................................................ 442
Chain Transfer ...................................................................................................... 443
Interrupt Sources................................................................................................... 444
Operation Timing.................................................................................................. 444
Number of DTC Execution States ........................................................................ 445
Activation by Interrupt.......................................................................................... 447
Activation by Software ......................................................................................... 447
Rev.7.00 Mar. 18, 2009 page xxix of lxvi
REJ09B0109-0700