HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 413

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

DREQ Pin Low Level Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel
for which the DREQ pin is selected.
Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low
level.
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer
Address bus
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMAC cycle is started.
[4] [7] Acceptance is resumed after the single cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
DMA control
Channel
DREQ
DACK
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
φ
Idle
[1]
Request
Bus release
Minimum of
2 cycles
[2]
[3]
Single
Request clear
Transfer source/
DMA single
destination
period
Acceptance resumes
Idle
[4]
Rev.7.00 Mar. 18, 2009 page 345 of 1136
Request
Bus release
Minimum of
2 cycles
[5]
Section 7 DMA Controller (DMAC)
[6]
Single
Request clear
DMA single
Transfer source/
period
destination
Acceptance resumes
Idle
REJ09B0109-0700
[7]
release
Bus