HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 749

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

14.3.3
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
but not by the WDT internal reset signal caused by overflows.
Bit
7
6
5
4
to
0
Note:
Bit Name
WOVF
RSTE
—
—
* Only a write of 0 is permitted, to clear the flag.
Reset Control/Status Register (RSTCSR)
Initial Value
0
0
0
All 1
R/W
R/(W) *
R/W
R/W
—
Description
Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode, and only 0 can be written.
[Setting condition]
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1, and
then writing 0 to WOVF
Reset Enable
Specifies whether or not a reset signal is generated
in the chip if TCNT overflows during watchdog
timer operation.
0: Reset signal is not generated even if TCNT
1: Reset signal is generated if TCNT overflows
Reserved
Can be read and written, but does not affect
operation.
Reserved
These bits are always read as 1 and cannot be
modified.
overflows
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
Rev.7.00 Mar. 18, 2009 page 681 of 1136
Section 14 Watchdog Timer (WDT)
REJ09B0109-0700