HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 63

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 9.6
Table 9.7
Table 9.8
Section 10 I/O Ports ...........................................................................................455
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Section 11 16-Bit Timer Pulse Unit (TPU)........................................................545
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Table 11.6
Table 11.7
Table 11.8
Table 11.9
Table 11.10 TPSC2 to TPSC0 (Channel 5)................................................................................. 556
Table 11.11 MD3 to MD0........................................................................................................... 558
Table 11.12 TIORH_0................................................................................................................. 560
Table 11.13 TIORL_0 ................................................................................................................. 561
Table 11.14 TIOR_1 ................................................................................................................... 562
Table 11.15 TIOR_2 ................................................................................................................... 563
Table 11.16 TIORH_3................................................................................................................. 564
Table 11.17 TIORL_3 ................................................................................................................. 565
Table 11.18 TIOR_4 ................................................................................................................... 566
Table 11.19 TIOR_5 ................................................................................................................... 567
Table 11.20 TIORH_0................................................................................................................. 568
Table 11.21 TIORL_0 ................................................................................................................. 569
Table 11.22 TIOR_1 ................................................................................................................... 570
Table 11.23 TIOR_2 ................................................................................................................... 571
Table 11.24 TIORH_3................................................................................................................. 572
Table 11.25 TIORL_3 ................................................................................................................. 573
Table 11.26 TIOR_4 ................................................................................................................... 574
Table 11.27 TIOR_5 ................................................................................................................... 575
Table 11.28 Register Combinations in Buffer Operation............................................................ 592
Register Function in Block Transfer Mode ............................................................. 442
DTC Execution Status ............................................................................................. 446
Number of States Required for Each Execution Status ........................................... 446
Port Functions ......................................................................................................... 456
Input Pull-Up MOS States (Port A)......................................................................... 512
Input Pull-Up MOS States (Port B)......................................................................... 516
Input Pull-Up MOS States (Port C)........................................................................ 520
Input Pull-Up MOS States (Port D)......................................................................... 524
Input Pull-Up MOS States (Port E) ......................................................................... 528
TPU Functions......................................................................................................... 546
Pin Configuration .................................................................................................... 549
CCLR2 to CCLR0 (Channels 0 and 3).................................................................... 553
CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)........................................................... 553
TPSC2 to TPSC0 (Channel 0)................................................................................. 554
TPSC2 to TPSC0 (Channel 1)................................................................................. 554
TPSC2 to TPSC0 (Channel 2)................................................................................. 555
TPSC2 to TPSC0 (Channel 3)................................................................................. 555
TPSC2 to TPSC0 (Channel 4)................................................................................. 556
Rev.7.00 Mar. 18, 2009 page lxi of lxvi
REJ09B0109-0700