HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 626

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 16-Bit Timer Pulse Unit (TPU)
Table 11.11 MD3 to MD0
Bit 3
MD3 *
0
1
Legend: ×: Don’t care
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
11.3.3
TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for
channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected
by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
Rev.7.00 Mar. 18, 2009 page 558 of 1136
REJ09B0109-0700
1
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
Bit 2
MD2 *
0
1
×
Timer I/O Control Register (TIOR)
be written to MD2.
2
Bit 1
MD1
0
1
0
1
×
Bit 0
MD0
0
1
0
1
0
1
0
1
×
Description
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
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