HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 218

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller (BSC)
6.3.4
RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access.
Bit
7
6
5
4
3
2
1
0
Rev.7.00 Mar. 18, 2009 page 150 of 1136
REJ09B0109-0700
RDNn = 0
RDNn = 1
Bit Name
RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)
Read Strobe Timing Control Register (RDNCR)
φ
RD
Data
RD
Data
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
T
1
Description
Read Strobe Timing Control 7 to 0
These bits set the negation timing of the read
strobe in a corresponding area read access.
As shown in figure 6.2, the read strobe for an area
for which the RDNn bit is set to 1 is negated one
half-state earlier than that for an area for which the
RDNn bit is cleared to 0. The read data setup and
hold time specifications are also one half-state
earlier.
0: In an area n read access, the RD is negated at
1: In an area n read access, the RD is negated one
the end of the read cycle
half-state before the end of the read cycle
Bus cycle
T
2
T
3
(n = 7 to 0)