HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 263

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

space to be output from a dedicated OE pin. In this case, the OE signal for DRAM space is output
from both the RD pin and the (OE) pin, but in external read cycles for other than DRAM space,
the signal is output only from the RD pin.
6.6.6
The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit
to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width,
etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.22
shows an example of the timing when a 3-state column address output cycle is selected.
Read
Write
Note: n = 2 to 5
Figure 6.22 Example of Access Timing with 3-State Column Address Output Cycle
Column Address Output Cycle Control
φ
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
T
p
Row address
(RAST = 0)
High
High
T
r
Rev.7.00 Mar. 18, 2009 page 195 of 1136
T
c1
Column address
Section 6 Bus Controller (BSC)
T
c2
REJ09B0109-0700
T
c3