HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 449

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus master during burst transfer. If there is no bus request, burst transfer is executed even if the
BGUP bit is set to 1.
Figure 8.6 shows examples of the timing in burst mode.
8.4.5
There are two transfer modes: normal transfer mode and block transfer mode. When the activation
source is an external request, either normal transfer mode or block transfer mode can be selected.
When the activation source is an auto request, normal transfer mode is used.
Normal Transfer Mode: In normal transfer mode, transfer of one transfer unit is processed in
response to one transfer request. EDTCR functions as a 24-bit transfer counter.
The ETEND signal is output only for the last DMA transfer. The EDRAK signal is output each
time a transfer request is accepted and transfer processing is started.
Figure 8.7 shows examples of DMA transfer timing in normal transfer mode.
Bus cycle
Bus cycle
Transfer conditions:
Transfer conditions:
Auto request mode, BGUP = 0
Auto request mode, BGUP = 1
Transfer Modes
CPU
CPU
Figure 8.6 Examples of Timing in Burst Mode
EXDMAC
CPU
EXDMAC
EXDMAC operates alternately with CPU
CPU
EXDMAC
EXDMAC
CPU cycle not generated
Rev.7.00 Mar. 18, 2009 page 381 of 1136
Section 8 EXDMA Controller (EXDMAC)
EXDMAC
CPU
EXDMAC
CPU
REJ09B0109-0700
CPU
CPU