HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 990

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 21 Flash Memory (0.18-μm F-ZTAT Version)
The FLER bit is set in the following conditions:
1. When an interrupt such as NMI occurs during programming/erasing.
2. When the flash memory is read during programming/erasing (including a vector read or an
3. When a SLEEP instruction (including software-standby mode) is executed during
4. When a bus master other than the CPU such as the DMAC or DTC gets bus mastership during
Error protection is cancelled only by a power-on reset or by hardware-standby mode. Note that the
reset should only be released after providing a reset input over a period longer than the normal 100
μs period. Since high voltages are applied during programming/erasing of the flash memory, some
voltage may remain after the error-protection state has been entered. For this reason, it is
necessary to reduce the risk of damage to the flash memory by extending the reset period so that
the charge is released.
The state-transition diagram in figure 21.15 shows transitions to and from the error-protection
state.
Rev.7.00 Mar. 18, 2009 page 922 of 1136
REJ09B0109-0700
Error occurrence
instruction fetch).
programming/erasing.
programming/erasing.
Programming/erasing
Programming/erasing disabled
enabled FLER = 0
Error protection mode
Program mode
Read disabled
Erase mode
Read enabled
FLER = 1
Figure 21.15 Transitions to Error-Protection State
Software-standby mode
software-standby mode
RES = 0 or STBY = 0
Cancel
programming/erasing disabled
RES = 0 or
STBY = 0
Error-protection mode
(Software standby)
Program/erase interface
register is in its initial state.
Programming/erasing disabled
Read disabled
(Hardware protection)
FLER = 1
Reset or standby
Read disabled
FLER = 0
Program/erase interface
register is in its initial state.