HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 414

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HD6412373R

Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 7 DMA Controller (DMAC)
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
7.5.11
DMAC internal-to-external dual address transfers and single address transfers can be executed at
high speed using the write data buffer function, enabling system throughput to be improved.
When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer
function, dual address transfer external write cycles or single address transfer and internal accesses
(on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are
independent of the bus mastership, and DMAC dead cycles are regarded as internal accesses.
A low level can always be output from the TEND pin if the bus cycle in which a low level is to be
output from the TEND pin is an external bus cycle. However, a low level is not output from the
TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal
bus cycle, and an external write cycle is executed in parallel with this cycle.
Figure 7.32 shows an example of dual address transfer using the write data buffer function. The
data is transferred from on-chip RAM to external memory.
Rev.7.00 Mar. 18, 2009 page 346 of 1136
REJ09B0109-0700
Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function
Internal read signal
External address
Internal address
Write Data Buffer Function
HWR, LWR
TEND
φ
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA
write
DMA
dead

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