HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 29

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.8
6.9
6.10 Write Data Buffer Function ............................................................................................... 268
6.11 Bus Release........................................................................................................................ 269
6.12 Bus Arbitration................................................................................................................... 274
6.13 Bus Controller Operation in Reset ..................................................................................... 276
6.14 Usage Notes ....................................................................................................................... 277
Section 7 DMA Controller (DMAC) .................................................................279
7.1
7.2
7.3
7.4
7.5
Burst ROM Interface.......................................................................................................... 246
6.8.1
6.8.2
6.8.3
Idle Cycle ........................................................................................................................... 249
6.9.1
6.9.2
6.11.1 Operation .............................................................................................................. 270
6.11.2 Pin States in External Bus Released State............................................................. 271
6.11.3 Transition Timing ................................................................................................. 272
6.12.1 Operation .............................................................................................................. 274
6.12.2 Bus Transfer Timing ............................................................................................. 275
6.14.1 External Bus Release Function and All-Module-Clocks-Stopped Mode.............. 277
6.14.2 External Bus Release Function and Software Standby ......................................... 277
6.14.3 External Bus Release Function and CBR Refreshing/Auto Refreshing................ 277
6.14.4 BREQO Output Timing ........................................................................................ 278
6.14.5 Notes on Usage of the Synchronous DRAM ........................................................ 278
Features .............................................................................................................................. 279
Input/Output Pins ............................................................................................................... 281
Register Descriptions ......................................................................................................... 281
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
Activation Sources ............................................................................................................. 307
7.4.1
7.4.2
7.4.3
Operation............................................................................................................................ 309
7.5.1
7.5.2
Basic Timing......................................................................................................... 246
Wait Control ......................................................................................................... 248
Write Access ......................................................................................................... 248
Operation .............................................................................................................. 249
Pin States in Idle Cycle ......................................................................................... 268
Memory Address Registers (MARA and MARB) ................................................ 283
I/O Address Registers (IOARA and IOARB) ....................................................... 283
Execute Transfer Count Registers (ETCRA and ETCRB) ................................... 284
DMA Control Registers (DMACRA and DMACRB) .......................................... 285
DMA Band Control Registers H and L (DMABCRH and DMABCRL).............. 293
DMA Write Enable Register (DMAWER) ........................................................... 304
DMA Terminal Control Register (DMATCR)...................................................... 306
Activation by Internal Interrupt Request............................................................... 308
Activation by External Request ............................................................................ 309
Activation by Auto-Request.................................................................................. 309
Transfer Modes ..................................................................................................... 309
Sequential Mode ................................................................................................... 312
Rev.7.00 Mar. 18, 2009 page xxvii of lxvi
REJ09B0109-0700