HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 403

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Full Address Mode (Block Transfer Mode): Figure 7.21 shows a transfer example in which
TEND output is enabled and word-size full address mode transfer (block transfer mode) is
performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
A one-block transfer is performed for a single transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-
state DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is generated
during data transfer, block transfer operation is not affected until data transfer for one block has
ended.
DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel
for which the DREQ pin is selected.
Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge.
Address bus
TEND
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)
HWR
Bus release
LWR
RD
φ
DMA
read
DMA
write
Block transfer
DMA
read
DMA
write
DMA
dead
Bus release
Rev.7.00 Mar. 18, 2009 page 335 of 1136
DMA
read
DMA
Section 7 DMA Controller (DMAC)
write
Last block transfer
DMA
read
DMA
write
REJ09B0109-0700
DMA
dead
Bus
release