HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 58

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 22 Masked ROM .................................................................................. 953
Figure 22.1 Block Diagram of 256-kbyte Masked ROM (HD6432375) .................................... 953
Section 23 Clock Pulse Generator ..................................................................... 955
Figure 23.1 Block Diagram of Clock Pulse Generator ............................................................... 955
Figure 23.2 Connection of Crystal Resonator (Example)........................................................... 958
Figure 23.3 Crystal Resonator Equivalent Circuit ...................................................................... 958
Figure 23.4 External Clock Input (Examples) ............................................................................ 959
Figure 23.5 External Clock Input Timing................................................................................... 960
Figure 23.6 Note on Board Design for Oscillation Circuit ......................................................... 963
Figure 23.7 Recommended External Circuitry for PLL Circuit ................................................. 963
Section 24 Power-Down Modes ........................................................................ 965
Figure 24.1 Mode Transitions..................................................................................................... 967
Figure 24.2 Software Standby Mode Application Example ....................................................... 976
Figure 24.3 Hardware Standby Mode Timing ............................................................................ 977
Figure 24.4 Hardware Standby Mode Timing when Power Is Supplied .................................... 978
Section 26 Electrical Characteristics ............................................................... 1019
Figure 26.1 Output Load Circuit .............................................................................................. 1023
Figure 26.2 System Clock Timing............................................................................................ 1067
Figure 26.3 SDRAMφ Timing.................................................................................................. 1067
Figure 26.4 (1) Oscillation Settling Timing................................................................................ 1068
Figure 26.4 (2) Oscillation Settling Timing................................................................................ 1068
Figure 26.5 Reset Input Timing................................................................................................ 1069
Figure 26.6 Interrupt Input Timing........................................................................................... 1069
Figure 26.7 Basic Bus Timing: Two-State Access ................................................................... 1070
Figure 26.8 Basic Bus Timing: Three-State Access ................................................................. 1071
Figure 26.9 Basic Bus Timing: Three-State Access, One Wait................................................ 1072
Figure 26.10 Basic Bus Timing: Two-State Access (CS Assertion Period Extended) ............... 1073
Figure 26.11 Basic Bus Timing: Three-State Access (CS Assertion Period Extended) ............. 1074
Figure 26.12 Burst ROM Access Timing: One-State Burst Access ........................................... 1075
Figure 26.13 Burst ROM Access Timing: Two-State Burst Access........................................... 1076
Figure 26.14 DRAM Access Timing: Two-State Access ........................................................... 1077
Figure 26.15 DRAM Access Timing: Two-State Access, One Wait.......................................... 1078
Figure 26.16 DRAM Access Timing: Two-State Burst Access ................................................. 1079
Figure 26.17 DRAM Access Timing: Three-State Access (RAST = 1) ..................................... 1080
Figure 26.18 DRAM Access Timing: Three-State Burst Access ............................................... 1081
Figure 26.19 CAS-Before-RAS Refresh Timing........................................................................ 1082
Figure 26.20 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) ........................... 1082
Figure 26.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0)............. 1083
Rev.7.00 Mar. 18, 2009 page lvi of lxvi
REJ09B0109-0700