HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 965
HD6412373R
Manufacturer Part Number
HD6412373R
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6412373R.pdf
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The procedures for download, initialization, and programming are shown in figure 21.11.
The procedure program must be executed in an area other than the flash memory to be
programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be
executed in the on-chip RAM.
Programming Procedure in User Program Mode
Set the FPEFEQ, FUBRA
JSR FTDAR setting + 32
Select on-chip program
to be downloaded and
destination by FTDAR
procedure program
Set SCO to 1 and
execute download
Start programming
specify download
Set FKEY to H'A5
Clear FKEY to 0
DPFR = 0?
Initialization
FPFR = 0?
parameter
a
Yes
Yes
Initialization error processing
Download error processing
Figure 21.11 Programming Procedure
No
No
1.
2.
3.
4.
5.
6.
7.
8.
Section 21 Flash Memory (0.18-μm F-ZTAT Version)
Rev.7.00 Mar. 18, 2009 page 897 of 1136
No
JSR FTDAR setting + 16
JSR FTDAR setting + 16
Disable interrupts and bus
Set parameters to ER1
Programming finished
(FMPAR and FMPDR)
procedure program
End programming
Set FKEY to H'5A
Clear FKEY to 0
master operation
programming is
other than CPU
Programming
Required data
FPFR = 0?
FPFR = 0?
processing
completed?
and ER0
a
Yes
Yes
Yes
REJ09B0109-0700
Clear FKEY and
Clear FKEY and
error processing
error processing
No
No
programming
programming
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