HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 411

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel
for which the DREQ pin is selected.
Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling
edge.
Address bus
DACK
TEND
HWR
LWR
φ
Figure 7.29 Example of Single Address Mode Transfer (Word Write)
release
Bus
DMA write
release
Bus
DMA write
Rev.7.00 Mar. 18, 2009 page 343 of 1136
release
Bus
Section 7 DMA Controller (DMAC)
Last transfer
DMA write
cycle
REJ09B0109-0700
DMA
dead
release
Bus