HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 793

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

15.4.2
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched at the middle of each bit by sampling the data at
the rising edge of the 8th pulse of the basic clock as shown in figure 15.3. Thus the reception
margin in asynchronous mode is given by formula (1) below.
Where M: Reception Margin
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula
below.
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Internal base
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = { (0.5 –
N: Ratio of bit rate to clock (N = 16)
D: Clock duty cycle (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode
0
2N
8 clocks
Start bit
1
) – (L – 0.5) F –
16 clocks
7
Section 15 Serial Communication Interface (SCI, IrDA)
⏐D – 0.5⏐
N
15 0
Rev.7.00 Mar. 18, 2009 page 725 of 1136
(1 + F) } × 100 [%]
D0
7
... Formula (1)
REJ09B0109-0700
15 0
D1