HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 512

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Data Transfer Controller (DTC)
9.5.5
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,
the interrupt set as the activation source is generated. These interrupts to the CPU are subject to
CPU mask level and interrupt controller priority level control.
In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)
is generated.
When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers has
ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is
generated. The interrupt handling routine should clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
9.5.6
Rev.7.00 Mar. 18, 2009 page 444 of 1136
REJ09B0109-0700
DTC activation
request
DTC
request
Address
φ
Figure 9.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
Interrupt Sources
Operation Timing
Vector read
information read
Transfer
Data transfer
Read Write
information write
Transfer