HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 323

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space
Access: In a continuous synchronous DRAM space access following a normal space access, the
settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of
consecutive reads in different areas, for example, if the second read is a full access to continuous
synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not. The timing in this case
is shown in figure 6.72.
Note: In the H8S/2378 Group, the synchronous DRAM interface is not supported.
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML
differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures
Figure 6.72 Example of Synchronous DRAM Full Access after External Read
Precharge-sel
DQMU, DQML
Address bus
Data bus
CKE
CAS
RAS
WE
RD
φ
External space read
T
1
NOP
T
(CAS Latency 2)
2
T
3
PALL ACTV
Column
address
T
Synchronous DRAM space read
p
Rev.7.00 Mar. 18, 2009 page 255 of 1136
address
address
Row
Row
T
r
READ
T
c1
Column address
Section 6 Bus Controller (BSC)
T
cl
NOP
T
c2
REJ09B0109-0700