HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 257

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.5.6
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert
states in which only the CS, AS, and address signals are asserted before and after a basic bus space
access cycle. Extension of the CS assertion period can be set for individual areas. With the CS
assertion extension period in write access, the data setup and hold times are less stringent since the
write data is output to the data bus.
RDNn = 0
RDNn = 1
Extension of Chip Select (CS) Assertion Period
φ
Address bus
CSn
AS
RD
Data bus
RD
Data bus
DACK,
EDACK
Figure 6.19 Example of Read Strobe Timing
T
1
Rev.7.00 Mar. 18, 2009 page 189 of 1136
Bus cycle
T
2
Section 6 Bus Controller (BSC)
REJ09B0109-0700
T
3