HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 271

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

6.6.11
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making
consecutive accesses to the same row address. This mode enables fast (burst) access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.
Burst Access (Fast Page Mode): Figures 6.30 and 6.31 show the operation timing for burst
access. When there are consecutive access cycles for DRAM space, the CAS signal and column
address output cycles (two states) continue as long as the row address is the same for consecutive
access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in
DRAMCR.
Burst Operation
(Address shift size
set to 10 bits)
This LSI
Figure 6.29 Example of 2-CAS DRAM Connection
RASn (CSn)
HWR (WE)
D15 to D0
RD (OE)
UCAS
LCAS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
Rev.7.00 Mar. 18, 2009 page 203 of 1136
1-Mbyte × 16-bit configuration
RAS
UCAS
LCAS
WE
OE
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15 to D0
2-CAS type 16-Mbit DRAM
10-bit column address
Section 6 Bus Controller (BSC)
Row address input:
A9 to A0
Column address input:
A9 to A0
REJ09B0109-0700