HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 374

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
7.3.7
DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can
be set for output automatically, and a transfer end signal output, by setting the appropriate bit. The
TEND pin is available only for channel B in short address mode. Except for the block transfer
mode, a transfer end signal asserts in the transfer cycle in which the transfer counter contents
reaches 0 regardless of the activation source. In the block transfer mode, a transfer end signal
asserts in the transfer cycle in which the block counter contents reaches 0.
Bit
7, 6
5
4
3
to
0
Rev.7.00 Mar. 18, 2009 page 306 of 1136
REJ09B0109-0700
Bit Name
⎯
TEE1
TEE0
⎯
DMA Terminal Control Register (DMATCR)
Initial Value
All 0
0
0
All 0
R/W
⎯
R/W
R/W
⎯
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Transfer End Enable 1
Enables or disables transfer end pin 1 (TEND1)
output.
0: TEND1 pin output disabled
1: TEND1 pin output enabled
Transfer End Enable 0
Enables or disables transfer end pin 0 (TEND0)
output.
0: TEND0 pin output disabled
1: TEND0 pin output enabled
Reserved
These bits are always read as 0 and cannot be
modified.