HD6412373R RENESAS [Renesas Technology Corp], HD6412373R Datasheet - Page 972

• Manufacturer Part Number: HD6412373R
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 21 Flash Memory (0.18-μm F-ZTAT Version)
(3)
The procedures for download, initialization, and erasing are shown in figure 21.12.
The procedure program must be executed in an area other than the user MAT to be erased.
Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in the
on-chip RAM.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 21.4.4, Procedure Program and Storable Area for
Programming Data.
For the downloaded on-chip program area, refer to figure 21.10.
Rev.7.00 Mar. 18, 2009 page 904 of 1136
REJ09B0109-0700
Erasing Procedure in User Program Mode
Set the FPEFEQ, FUBRA
JSR FTDAR setting + 32
Select on-chip program
to be downloaded and
destination by FTDAR
Start erasing procedure
Set SCO to 1 and
specify download
execute download
Set FKEY to H'A5
Clear FKEY to 0
Initialization
FPFR = 0 ?
DPFR = 0?
parameter
program
a
Yes
Yes
Initialization error processing
Download error processing
No
No
1.
Figure 21.12 Erasing Procedure
No
JSR FTDAR setting + 16
Disable interrupts and
bus master operation
Set FEBS parameter
procedure program
Set FKEY to H'5A
Clear FKEY to 0
other than CPU
Required block
End erasing
FPFR = 0?
completed?
erasing is
Erasing
a
Yes
Yes
Clear FKEY and erasing
No
error processing
2.
3.
4.
5.
6.